EE457 Final

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Digital Logic Lab

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std_logic_vector

Collection of 1's and 0's

Signed and Unsigned

Number values

Signed signifies positive or negative with left most bit (1 = negative, 0 = positive)

Executive Summary

Describe the project so that non-technical people can understand how it works

Variable

Instantly changed everywhere ( := )

Entities vs. Architecture

Entities - Tells what the ports and inputs are

Architecture - Describes whats going on with the entity (declares signals)

Signals

Signals are REGISTERS

Process

Keeps commands in parallel
(able to run simultaneously)

State Machines

Three Parts:
Input Logic
State Transition
Output Logic
(all are parallel)

Mealy vs. Moore

Mealy - Output determined by current state and inputs

Moore - Output determined on current state only

Reset

Treat as a CLR
(take the CLK out of the reset so if the clock fails, reset will still work)

Why use FPGA?

Data throughput
Parallelism
Timing

FIFO

First in First out - used to sync 2 clocks of same frequency but different domain

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